1. Field of the Invention
The present invention relates to a single-sided random access memory (RAM) cell and a method of writing data values to the same.
2. Discussion of Related Art
FIG. 1 is a circuit diagram of a conventional single-sided five transistor RAM cell 100 which is commonly used in integrated circuits such as field programmable gate arrays (FPGAs). As used herein, a single-sided RAM cell is a RAM cell which is accessed by a single line during a write operation, and which is accessed by a single line during a read operation. Single-sided RAM cell 100 includes n-channel access transistor 101, p-channel transistors 102-103, and n-channel transistors 104-105. P-channel transistor 102 and n-channel transistor 104 are coupled between the V.sub.cc and ground voltage supplies as illustrated to form a first inverter 106. Similarly, p-channel transistor 103 and n-channel transistor 105 are coupled between the V.sub.cc and ground voltage supplies to form a second inverter 107. Inverters 106 and 107 are cross-coupled to form data latch 108. The output terminal of first inverter 106 and the input terminal of second inverter 107 are connected at node N1. Node N1 is also connected to the drain of access transistor 101. The output terminal of second inverter 107 and the input terminal of first inverter 106 are connected at node N2. Node N2 provides the output signal of RAM cell 100.
A data value is written to RAM cell 100 by asserting a logic high write control signal W on the gate of access transistor 101, thereby turning on transistor 101. When access transistor 101 is turned on, a data value D.sub.IN is applied to the source of access transistor 101. The data value D.sub.IN is thereby routed through access transistor 101 and applied to node N1.
RAM cell 100 can be in a logic high state or a logic low state. In the logic low state, node N1 is at a logic low voltage (i.e., n-channel transistor 104 is turned on and p-channel transistor 102 is turned off), and node N2 is at a logic high voltage (i.e., p-channel transistor 103 is turned on and n-channel transistor 105 is turned off). In the logic high state, node N1 is at a logic high voltage (i.e., p-channel transistor 102 is turned on and n-channel transistor 104 is turned off), and node N2 is at a logic low voltage (i.e., n-channel transistor 105 is turned on and p-channel transistor 103 is turned off).
To write a logic 1 value to RAM cell 100 while RAM cell 100 is in a logic low state, the write control signal W is asserted high, and a logic high data value D.sub.IN is applied to the source of access transistor 101. The logic high data value D.sub.IN typically has a voltage of Vcc. At low operating voltages, V.sub.cc (and therefore D.sub.IN) can be less than 2.5 Volts. Under these conditions, a relatively small voltage is developed across n-channel transistor 104, since the voltage developed across n-channel transistor 104 is equal to the voltage of D.sub.IN (e.g., 2.5 Volts) minus the threshold voltage drop across access transistor 101 (e.g., 1 volt). Consequently, for low operating voltages, the voltage developed across n-channel transistor 104 may be insufficient to reliably cause RAM cell 100 to transition from a logic low state to a logic high state. That is, the voltage across n-channel transistor 104 may be insufficient to pull node N1 up high enough to turn on n-channel transistor 105. If transistor 101 is fabricated using a deep sub-micron process, the n-channel threshold voltage does not scale down with the decrease in the operation voltage, thereby further exacerbating the problem.
Writing a logic low data value D.sub.IN to RAM cell 100 is relatively easy because a logic low data value D.sub.IN does not experience a threshold voltage drop across access transistor 101. As a result, the logic low voltage applied to node N1 readily causes p-channel transistor 103 to turn on, thereby causing RAM cell 100 to enter a logic low state.
FIG. 2 is a circuit diagram of a conventional writing-decoding system 200 for use with sixteen single-sided RAM cells 100A-100P. Each of single-sided RAM cells 100A-100P includes a corresponding access transistor 101A-101P and a corresponding data latch 108A-108P. Each of single-sided RAM cells 100A-100P is identical to previously described single-sided RAM cell 100 (FIG. 1). Writing-decoding system 200 further includes access transistors 201-221 and inverters 231-239 as illustrated. Address signals A7-AO are applied to inverters 231-238, respectively. Data input signal D.sub.IN is routed through access transistor 221 to inverter 239 when the write enable signal W is asserted high. The output signal of inverter 239 is provided to each of access transistors. 201-204. One of the address signals A7-A4 is asserted low, thereby causing the output signal from inverter 239 to be routed through one of access transistors 201-204. Each of access transistors 201-204 is coupled to four corresponding access transistors. For example in this embodiment, access transistor 201 is coupled to access transistors 205-208, access transistor 202 is coupled to access transistors 209-212, access transistor 203 is coupled to access transistors 213-216, and access transistor 204 is coupled to access transistors 217-220. Each of access transistors 205-220 is coupled to a corresponding RAM cell 100A-100P. One of the address signals A3-AO is asserted low, thereby causing the output signal provided by inverter 239 to be routed to one of memory cells 100A-100P. The write select signal WS is asserted high to provide access to a first node (i.e., node N1 of FIG. 1) within each of memory cells 100A-100P. Thus, RAM cell 100A is addressed by setting address signals A7-AO to 01110111, respectively, and setting the signal WS to 1. The D.sub.IN signal is stored in the addressed RAM cell in the manner previously described in reference to FIG. 1. However, decoding-address system 200 fails to remedy the difficulties encountered when writing a logic high data value to a single-sided RAM cell which is currently in a logic low state.
FIG. 3 is a circuit diagram of a conventional double-sided static RAM (SRAM) cell 200. As used herein, a double-sided memory cell is a memory cell which is written by a pair of input lines, and which is read by a pair of output lines. The input lines can be common with the output lines. Because double-sided SRAM cell 200 includes elements similar to RAM cell 100, similar elements in FIGS. 1 and 3 are labeled with similar reference numbers. Thus, in addition to n-channel access transistor 101, p-channel transistors 102-103 and n-channel transistors 104-105, SRAM cell 200 includes a second n-channel access transistor 201. Data values are written to SRAM cell 200 by asserting a logic high control signal W on the gates of access transistors 101 and 201, and providing a data value D.sub.IN and a complementary data value D.sub.IN bar to the sources of access transistors 101 and 201, respectively. Because a logic low value is always applied to either node N1 or node N2 during a write operation, SRAM cell 200 easily transitions between logic states. However, the second access transistor 201 causes double-sided SRA cell 200 to have a greater layout area than single-sided RAM cell 100.
It would therefore be desirable to have a single-sided memory cell which is capable of being reliably written, regardless of the current state of the memory cell and the value of the data value being written to the memory cell.